Installing Intel MPSS 3.3 in Arch Linux

by Andrey Vladimirov 20. August 2014 16:35

Complete Paper: PDF logo Colfax_MPSS_in_Arch_Linux.pdf (97 KB)

This technical publication provides instructions for installing the Intel Manycore Platform Software Stack (MPSS) version 3.3 in Arch Linux operating system. Intel MPSS is a suite of tools necessary for operation of Intel Xeon Phi coprocessors. Instructions provided here enable offload and networking functionality for coprocessors in Arch Linux. The procedure described in this paper is completely reversible via an uninstallation script.

Downloads:

Product Direct Link
Intel MPSS 3.3 (page, archive) mpss-3.3-linux.tar (~400 MB)
Linux Kernel 3.10 LTS (AUR) linux-lts310.tar.gz (78 KB)
TRee Installation Generator (TRIG) trig.sh (3 KB)
RHEL networking utilities rhnet.tgz (33 KB)
Offload functionality test Offload-Hello.cc (347 B)
GNU Public License v2 (applies to TRIG and RHEL utilities) page

Complete Paper: PDF logo Colfax_MPSS_in_Arch_Linux.pdf (97 KB)

Make sure to read important additional information by clicking "Comments" below ↓

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File I/O on Intel Xeon Phi Coprocessors: RAM disks, VirtIO, NFS and Lustre

by Andrey Vladimirov 28. July 2014 13:10

Complete Paper: PDF logo Colfax_File_IO_on_Intel_Xeon_Phi_Coprocessors.pdf (2.27 mb)

The key innovation brought about by Intel Xeon Phi coprocessors is the possibility to port most HPC applications to manycore computing accelerators without code modification. One of the reasons why this is possible is support for file input/output (I/O) directly from applications running on coprocessors. These facilities allow seamless usage of manycore accelerators in common HPC tasks such as application initialization from file data, saving running output, checkpointing and restarting, data post-processing and visualization, and other.

This paper provides information and benchmarks necessary to make the choice of the best file system for a given application from a number of the available options:

  • RAM disks,
  • virtualized local hard drives, and
  • distributed storage shared with NFS or Lustre.

We report benchmarks of I/O performance and parallel scalability on Intel Xeon Phi coprocessors, strengths and limitations of each option. In addition, the paper presents system administration procedures necessary for using each file system on coprocessors, including bridged networking and InfiniBand configuration, software installation and MPSS image modifications. We also discuss the applicability of each storage option to common HPC tasks.

Complete Paper: PDF logo Colfax_File_IO_on_Intel_Xeon_Phi_Coprocessors.pdf (2.27 mb)

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Colfax Research papers translated to Japanese

by Andrey Vladimirov 14. July 2014 12:21

With the help of our partners at Intel, some of our articles on Intel Xeon Phi coprocessor programming were translated to the Japanese language.

インテル社の協力で、我が社のインテル(R) Xeon Phi(TM) コプロセッサーのプログラミングについての論文の一部が日本語に翻訳されました。

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Cluster-Level Tuning of a Shallow Water Equation Solver on the Intel MIC Architecture

by Andrey Vladimirov 12. May 2014 09:55

Complete Paper: PDF logo Colfax_Shallow_Water.pdf (810.35 kb)

The paper demonstrates the optimization of the execution environment of a hybrid OpenMP+MPI computational fluid dynamics code (shallow water equation solver) on a cluster enabled with Intel Xeon Phi coprocessors. The discussion includes:

  1. Controlling the number and affinity of OpenMP threads to optimize access to memory bandwidth;
  2. Tuning the inter-operation of OpenMP and MPI to partition the problem for better data locality;
  3. Ordering the MPI ranks in a way that directs some of the traffic into faster communication channels;
  4. Using efficient peer-to-peer communication between Xeon Phi coprocessors based on the InfiniBand fabric.

With tuning, the application has 90% percent efficiency of parallel scaling up to 8 Intel Xeon Phi coprocessors in 2 compute nodes. For larger problems, scalability is even better, because of the greater computation to communication ratio. However, problems of that size do not fit in the memory of one coprocessor.

The performance of the solver on one Intel Xeon Phi coprocessor 7120P exceeds the performance on a dual-socket Intel Xeon E5-2697 v2 CPU by a factor of 1.6x. In a 2-node cluster with 4 coprocessors per compute node, the MIC architecture yields 5.8x more performance than the CPUs.

Only one line of legacy Fortran code had to be changed in order to achieve the reported performance on the MIC architecture (not counting changes to the command-line interface).

The methodology discussed in this paper is directly applicable to other bandwidth-bound stencil algorithms utilizing a hybrid OpenMP+MPI approach.

Complete Paper: PDF logo Colfax_Shallow_Water.pdf (810.35 kb)

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Configuration and Benchmarks of Peer-to-Peer Communication over Gigabit Ethernet and InfiniBand in a Cluster with Intel Xeon Phi Coprocessors

by Vadim Karpusenko 11. March 2014 14:05

Complete Paper: PDF logo Colfax_InfiniBand_for_MIC.pdf (2.32 mb)

Intel Xeon Phi coprocessors allow symmetric heterogeneous clustering models, in which MPI processes are run fully on coprocessors, as opposed to offload-based clustering. These symmetric models are attractive, because they allow effortless porting of CPU-based applications to clusters with manycore computing accelerators.

However, with the default software configuration and without specialized networking hardware, peer-to-peer communication between coprocessors in a cluster is quenched by orders of magnitude compared to the capabilities of Gigabit Ethernet networking hardware. This situation is remedied by InfiniBand interconnects and the software supporting them.

In this paper we demonstrate the procedures for configuring a cluster with Intel Xeon Phi coprocessors connected with Gigabit Ethernet as well as InfiniBand interconnects. We measure and discuss the latencies and bandwidths of MPI messages with and without the advanced configuration with InfiniBand support. The paper contains a discussion of MPI application tuning in an InfiniBand-enabled cluster with Intel Xeon Phi Coprocessors, a case study of the impact of InfiniBand protocol, and a set of recommendations for accommodating the non-uniform RDMA performance across the PCIe bus in high performance computing applications.

Complete Paper: PDF logo Colfax_InfiniBand_for_MIC.pdf (2.32 mb)

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Primer on Computing with Intel Xeon Phi Coprocessors

by Andrey Vladimirov 6. March 2014 14:35

Presentation slides: PDF logo Colfax-G4-XeonPhi-Presentation.pdf (10.31 mb)

Geant4 is a high energy physics application package for simulation of elementary particle transport through matter. It is used in fundamental physics experiments, as well as in industrial and medical applications. For example, the ATLAS detector at LHC and the Fermi Gamma-Ray Space Telescope rely on Geant4 simulations, DNA damage due to ionizing radiation is studied by a derivative project Geant4-DNA, and radiotherapy planning can benefit from calculations with Geant4.

Geant4 has long been employing distributed-memory parallelism in the MPI framework. However, due to the trend of increasing ratio of core count to memory size in modern computing systems, and due to the need to process larger geometry models, Geant4 is undergoing modernization through inclusion of thread parallelism in shared memory. This effort is led by SLAC researchers Dr. Makoto Asai and Dr. Andrea Dotti (see, e.g., slides 1 and slides 2).

A beneficial by-product of such modernization is the possibility to use the Intel Many Integrated Core (MIC) architecture of Intel Xeon Phi coprocessors for Geant4 calculations. This possibility is being actively investigated by Dr. Dotti, who has extensively discussed his work on this project with us at Colfax.

I was fortunate to be invited to give a presentation for Geant4 users at the SLAC Geant4 Tutorial 2014 held at Stanford University. The talk discusses the Intel Many Integrated Core Architecture and points to the resources for learning about optimization of computing applications for Intel Xeon Phi coprocessors. The slides of the talk can be downloaded from this page.

Presentation slides: PDF logo Colfax-G4-XeonPhi-Presentation.pdf (10.31 mb)

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"Heterochromic" Computer and Finding the Optimal System Configuration for Medical Device Engineering

by Andrey Vladimirov 27. January 2014 09:55

Report: PDF logo Carestream_HPC_Study-December2013.pdf (4.01 mb)

Designing a computing system configuration for optimal performance of a given task is always challenging, especially if the acquisition budget is fixed. It is difficult, if not impossible, to analytically resolve all of the following questions:

  • How well does the application scale across multiple cores?
  • What is the efficiency and scalability of the application with accelerators (GPGPUs or coprocessors)?
  • Should measures be taken to prevent I/O bottlenecks?
  • Is it more efficient to scale up a single task or partition the system for multiple tasks?
  • What combination of CPU models, accelerator count, and per-core software licenses gives the best return on investment?

Rigorous benchmarking is the most reliable method of ensuring the "best bang for buck", however, it requires access to the computing systems of interest. Colfax takes pride in being able to offer interested customers opportunities for deducing the optimal configuration for specific tasks.

Recently we received a request from Peter Newman, Systems Engineer at Carestream Health, for evaluating the performance of the software tool ANSYS Mechanical on Colfax's computing solutions. His goal was to find the optimum number of computing accelerators (if any) and software licenses that he needed to purchase in order to achieve the best performance of specific calculations in ANSYS.

In order to allow Mr. Newman to seamlessly benchmark a variety of system configurations, we provided him access to a unique machine built by Colfax, based on an Intel Xeon E5 CPU, and supporting four Nvidia Tesla K40 GPGPUs and four Intel Xeon Phi 7120P coprocessors. Normally, this system is built either with eight GPGPUs as CXT9000, or outfitted with eight Xeon Phi coprocessors as CXP9000. However, the ``heterochromic'' (i.e., featuring both Nvidia's and Intel's accelerators) configuration that we produced for this project allowed the customer to benchmark the ANSYS software on both the Nividia Tesla and Intel Xeon Phi platforms with minimal logistic effort. Indeed, the software had to be installed only once, and the benchmark scripts and data collection scripts could all be retained in one place.

The methodology of the study was developed by Peter Newman, who also executed the benchmarks, collected and analyzed the data, and summarized findings in a comprehensive report. Mr. Jason Zbick of SimuTech Group, an ANSYS distributor, participated in the study and provided support for ANSYS Mechanical installation and configuration. Colfax's involvement included custom system configuration, maintenance of secure remote access to the system and assistance with automated result collection.

The result of the testing, pertinent to the current state of the software and the specific models used in Carestream, allowed Mr. Newman to empirically find the best way to spend the funds allocated for improvement of his computing infrastructure. His feedback was,
``This study greatly changed my plan for what to purchase with the budget I had to work with... Having all the hardware at once made the testing very efficient. That was the best part. ''

The customer has generously shared with us the report on his thorough research. The report can be downloaded below.

Report: PDF logo Carestream_HPC_Study-December2013.pdf (4.01 mb)

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Parallel Computing in the Search for New Physics at LHC

by Andrey Vladimirov 2. December 2013 15:35

Manuscript of Publication: PDF logo http://arxiv.org/pdf/1310.7556 (submitted to JINST)

Feature in International Journal of Innovation: PDF logo p36-38_Valerie_Halyo-LR.pdf (724.08 kb)

In the past few months we have had the pleasure of collaborating with Prof. Valerie Halyo of Princeton University on modernization of a high energy physics application for the needs of the Large Hadron Collider (LHC). The objective of our project is to improve the performance of the trigger at LHC, so as to enable real-time detection of exotic collision event products, such as black holes or jets.

For the numerical algorithm of the new trigger software, the Hough transform was chosen. This method allows fast detection of straight or curved tracks in a set of points (detector hits), which could be the traces of new exotic particles. The nature of the numerical Hough transform is highly parallelizable, however, existing implementations did not use hardware parallelism or used it sub-optimally.

Colfax's role in the project was to optimize a thread-parallel implementation of the Hough transform for multi-core processors. The result of our involvement was a code capable of detecting 5000 tracks in a synthetic dataset 250x faster than prior art, on a multi-core desktop CPU. By benchmarking the application on a server based on multi-core Intel Xeon E5 processors, we obtained a yet 5x greater performance. The techniques used for optimization, briefly discussed in the report paper (see below), are featured in our book on parallel programming and in our developer training program. They focus on code portability across multi- and many-core platforms, with the emphasis on future-proofing the optimized application.

Our results are reported in a publication submitted for peer review to JINST (see link at the top and bottom of this post). Prof. Halyo's work was also featured in an article in International Journal of Innovation, available for download here (courtesy of Prof. Halyo).

Manuscript of Publication: PDF logo http://arxiv.org/pdf/1310.7556 (submitted to JINST)

Feature in International Journal of Innovation: PDF logo p36-38_Valerie_Halyo-LR.pdf (724.08 kb)

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Accelerating Public Domain Applications: Lessons from Models of Radiation Transport in the Milky Way Galaxy

by Andrey Vladimirov 25. November 2013 10:53

Slides: PDF logo SC13-Intel-Theater-Talk-Colfax.pdf (2.62 mb)

Manuscript: PDF logo http://arxiv.org/pdf/1311.4627 (submitted to Computer Physics Communications)

Last week I had the privilege of giving a talk at the Intel Theater at SC'13. I presented a case study done with Stanford University on using Intel Xeon Phi coprocessors for accelerating a new astrophysical library HEATCODE (HEterogeneous Architecture library for sTochastic COsmic Dust Emissivity).

If this talk can be summarized in one sentence, that will be "One high performance code for two platforms is reality". Indeed, the optimizations performed in order to optimize HEATCODE for the MIC architecture lead to a tremendous performance increase on the CPU platform. As a consequence, we have developed a high performance library which can be employed and modified both by users who have access to Xeon Phi coprocessors, and by those only using multi-core CPUs.

The paper introducing HEATCODE library with details of the optimization process is under review at Computer Physics Communications. The preliminary manuscript can be obtained from arXiv, and the slides of the talk are available on this page (see links above and below). The open source code will be made available upon the acceptance of the paper.

Slides: PDF logo SC13-Intel-Theater-Talk-Colfax.pdf (2.62 mb)

Manuscript: PDF logo http://arxiv.org/pdf/1311.4627 (submitted to Computer Physics Communications)

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Heterogeneous Clustering with Homogeneous Code: Accelerate MPI Applications Without Code Surgery Using Intel Xeon Phi Coprocessors

by Andrey Vladimirov 17. October 2013 11:55

Complete Paper: PDF logo Colfax_Heterogeneous_Clustering_Xeon_Phi.pdf (442.87 kb)

This paper reports on our experience with a heterogeneous cluster execution environment, in which a distributed parallel application utilizes two types of compute devices: those employing general-purpose processors, and those based on computing accelerators known as Intel Xeon Phi coprocessors.

Unlike general-purpose graphics processing units (GPGPUs), Intel Xeon Phi coprocessors are able to execute native applications. In this mode, the application runs in the coprocessor's operating system, and does not require a host process executing on the CPU and offloading data to the accelerator (coprocessor). Therefore, for an application in the MPI framework, it is possible to run MPI processes directly on coprocessors. In this case, coprocessors behave like independent compute nodes in the cluster, with an MPI rank, peer-to-peer communication capability, and access to a network-shared file system. With such configuration, there is no need to instrument data offload in the application in order to utilize a heterogeneous system comprised of processors and coprocessors. That said, an MPI application designed for a CPU-only cluster can be used on coprocessor-enabled clusters without code modification.

We discuss the issues of portable code design, load balancing and system configuration (networking and MPI) necessary in order for such a setup to be efficient. An example application used for this study carries out a Monte Carlo simulation for Asian option pricing. The paper includes the performance metrics of this application with CPU-only and heterogeneous cluster configurations.

This visualization based on the paper was exhibited by Colfax at SC13 at the Intel corporate booth:

Complete Paper: PDF logo Colfax_Heterogeneous_Clustering_Xeon_Phi.pdf (442.87 kb)

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About Colfax Research

Colfax International provides an arsenal of novel computational tools, which need to be leveraged in order to harness their full power. We are collaborating with researchers in science and industry, including our customers, to produce case studies, white papers, and develop a wide knowledge base of the applications of current and future computational technologies.

This blog will contain a variety of information, from hardware benchmarks and HPC news highlights, to discussions of programming issues and reports on research projects carried out in our collaborations. In addition to our in-house research, we will present contributions from authors in the academia, industry and finance, as well as software developers. Our hope is that this information will be useful to a wide audience interested in innovative computing technologies and their applications.

Author Profiles

Andrey Vladimirov, PhD, is the Head of HPC Research at Colfax International. His primary research interest is the application of modern computing technologies to computationally demanding scientific problems. Prior to joining Colfax, Andrey was involved in theoretical astrophysics research at the Ioffe Institute (Russia), North Carolina State University, and Stanford University (USA), where he studied cosmic rays, collisionless plasmas and the interstellar medium using computer simulations. 

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Author Profiles

Vadim Karpusenko, PhD, is a Principal HPC Research Engineer at Colfax International. His research interests are in the area of physical modeling with HPC clusters, highly parallel architectures, and code optimization. Vadim holds a PhD in Physics from North Carolina State University for his computational research of the free energy and stability of helical secondary structures of proteins.

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